1. Field of the Invention
The invention relates generally to a chip packaging structure and a packaging process thereof. More particularly, the invention provides a chip packaging structure and a chip packaging process to increase the circuit layout density for high electrical performance.
2. Description of the Related Art
A flip chip interconnection structure usually consists of mounting a chip on a carrier substrate via a plurality of conductive bumps that electrically and mechanically connect the die pads of the chip to bump pads of the carrier substrate. Such an interconnection structure is particularly suitable for chip packages with a high pin count, and has the advantages of providing smaller surface areas and shorter electrical paths. Presently, two types of flip chip interconnection structures known in the art are a flip chip ball grid array (FC/BGA) package and a flip chip pin grid array (FC/PGA) package.
Referring to FIG. 1, a schematic view illustrates a structure of FC/BGA package known in the art. The FC/BGA package comprises a substrate 10, a chip 130, a plurality of conductive bumps 140, and a plurality of solder balls 150. The substrate 110 has a plurality of bump pads 116a formed on the side of top surface 112, and a plurality of contact pads 116b formed on an opposite bottom surface 114. The conductive bumps 140 electrically connect die pads 136 on the active surface 132 of the chip 130 to the bump pads 116a of the substrate 110. Meanwhile, The solder balls 150 are attached to the ball pads 116b of the substrate for external connection.
An underfill compound 160 is further formed in the gap between the active surface 132 of the chip 130 and the top surface 112 of the substrate 110 to seal and protect the conductive bumps 140 by sharing thermal strains due to a thermal mismatch between the substrate 110 and the chip 130.
As the dimensional size of the chip package is reduced, the surface area of the chip and the pitch between the bonding pads of the chip become increasingly smaller. In other words, the density of the die pads becomes higher. To adequately accommodate the density of the die pads of the chip, the substrate also has to be provided with a high density of bump pads and a finer circuit layout.
The known FC/BGA or FC/PGA package currently uses a substrate made of ceramic or organic based materials. It should be remarked that the organic substrate is more common. Due to a substantial thermal expansion of the organic material, the trace width and trace pitch currently obtainable inside the substrate are limited to be above 25 μm. Furthermore, due to the nature of its material, a maximal size of the blank (before cutting) of the organic substrate is limited to 610 mm×610 mm. The above technical limitations of the prior art are not satisfactory in view of current demands.